1. Field of the Invention
This invention is related to integrated circuits. More particularly, this invention relates to integrated circuit chips capable of having multiple packaging options.
2. Description of the Related Art
The Joint Electron Device Engineering Council (JEDEC) of the Electronic Industries Alliance (EIA) creates the semiconductor engineering standards for integrated circuits. The JEDEC standard No. 21-C defines the engineering specifications for solid state memories. The specifications include the electrical operating parameters and the physical packaging for the semiconductor memories that are generally available in the industry. A particular type of random access memory (RAM) may have multiple packaging options as shown in FIGS. 1a, 1b, 2a and 2b. FIG. 1a illustrates a 64M bit synchronous dynamic RAM (SDRAM) as shown in the JEDEC standard 21-C page 3.11.4-13; FIG. 1b illustrates an equivalent 64M bit SDRAM as shown in the JEDEC standard 21-C page 3.11.2-12 and FIG. 2a illustrates an equivalent 64M bit SDRAM as shown in the JEDEC standard 21-C page 3.11.4-4. FIG. 2b illustrates a 32K.times.32 Burst Static RAM (BSRAM) as shown in JEDEC standard 21-C page 3.7.8-5. In FIGS. 1a and 1b, the 64M bit SDRAM is packaged respectively in an 86 pin thin small outline package (TSOP) and a 66 pin TSOP and in FIG. 2a the 64M bit is packaged in a 100 pin thin profile plastic quad flat package (TQFP). In FIG. 2b a 32K.times.32 BSRAM is packaged in a 100 pin TQFP. As the size of the semiconductor memory chips has increased with time, the physical size of the semiconductor substrate has approached the physical size of the package. This has forced the input/output connection pads of the semiconductor memory to be connected directly to the pins of the package that are in closest proximity.
Refer now to FIGS. 3a and 3b for a view of the top surface of an SDRAM. The arrays of memory cells (MA) are placed at each end of the semiconductor substrate and the command and control circuitry is placed centrally on the semiconductor substrate. The command and control circuitry accepts the address signals, the clock signals, the row address strobe, the column address strobe, and the write/read command from external circuitry. The command and control circuitry generates the signals necessary to write data to or read data from the desired memory cells of the memory arrays.
The input/output connection pads are placed as near as possible to the functions for which the signals they are to conduct are located. For instance, the data (DQ) input/output connection pads are placed near the array of memory cells and the command and control input/output connection pads are placed near the command and control circuitry. Placing the input/output connection pads as close as possible to the circuitry that employs the signals present on the connection minimizes wiring complexity and attendant crosstalk and noise problems.
The physical structure of the circuit and the placement of the input/output connection pads is a design decision made by the manufacturer of a particular chip. In FIG. 3a, the input/output connection pads are placed at two peripheral edges of the SDRAM. While, in FIG. 3b, the input/output connection pads are placed about a central axis of the SDRAM. The placement of the data input/output (DQ) connection pads and the command and control input/output connection pads in the TSOP package of FIG. 1a or the TQFP package of FIG. 2b. This structure is termed in the art as an outer datalinner control package (ODIC). That is the data input/output pins are at the end regions of the TSOP package and the command and control input/output pins are centrally located on the edges of the TSOP or TQFP package.
FIGS. 4a and 4b illustrate top views of an SDRAM substrate, in which the command and control circuitry is placed at one edge of the semiconductor substrate, while the memory arrays (MA) occupy the remaining area of the semiconductor substrate.
The command and control input/output connection pads are now best placed at the edges of the semiconductor substrate nearest the command and control circuitry. Likewise, the data input/output (DQ) connection pads are placed along the remaining edges of the semiconductor substrate nearest the memory arrays.
This particular structure is best suited to fit the TSOP of FIG. 1b or TQFP package shown in FIG. 2a. The command and control input/output connection pads are bonded to the closest input/output pins of the TSOP of FIG. 1b or TQFP package shown in FIG. 2a. In this case, the command and control input/output pins are now at one end of the TSOP of FIG. 1b or TQFP package shown in FIG. 2a. The data input/output (DQ) connection pads are bonded to the closest input/output pins of the TSOP of FIG. 1b or TQFP package shown in FIG. 2a. The data input/output pins are at the remaining edges of the TSOP of FIG. 1b or TQFP package shown in FIG. 2a. This structure is termed in the art as a non-outer data inner control package (non-ODIC).
Any manufacturer of the RAM desiring to provide each of the two package styles, the TSOP and TQFP package, must have two separate RAM integrated circuit designs to fulfill demand for both styles.
U.S. Pat. No. 5,914,530 (Murakami et at.) describes an integrated circuit chip similar to that described in FIG. 3b and mounted in a TSOP package somewhat similar to that of FIG. 1. Murakami et al. further describes the placement and structure of the lead frame and the bonding from the lead frame to the semiconductor substrate.
U.S. Pat. No. 5,781,488 (Lia et al.) describes a DRAM having a staggered bit-line sense amplifier configuration. The stagger bit-line sense amplifier uses an input/output path that minimizes time delay through the input/output data path.
U.S. Pat. No. 5,843,809 (Rostoker) describes a lead frame structure for DRAM's employing trench capacitors. Rostoker illustrates the use of a lead frame using one or more Y-shaped leads, which branch in the direction of different input/output connection pins. This allows one of the module pins to connect to multiple widely spaced input/output connection pads. The lead frame is designed to be used in a dual-in-line package (DIP) with semiconductor substrates having input/output connection pads placed on the central axis of the substrate as shown in FIG. 3b.